The case is, of course, VLSI Technology LLC v. Intel Corp., unanimous panel opinion by Judge Taranto, joined by Judges Lourie and Dyk. (For previous mention on this blog of sources discussing the lower court ruling, see here and here.) In this action, VLSI asserted two patents, the ‘373 Patent titled “Minimum Memory Operating Voltage Technique,” and the ‘759 Patent, titled “System and Method of Managing Clock Speed in an Electronic Device.” The case was tried to a jury, which found both patents infringed and awarded $1.5 billion for the ‘373 Patent and $675 million for ‘759. On appeal, the Federal Circuit affirms the judgment of infringement as to ‘373 and reverses as to ‘759 (which in turn wipes out the damages awarded for the infringement of that patent). The court vacates the damages award as to ‘373. Given the subject matter of this blog, I will focus on the damages issues, which center on the adequacy of VLSI’s damages evidence.
As described by the court, to come up with a reasonable royalty estimate VLSI’s experts used a four-step process that “sought, without reliance on licenses, to identify the incremental value over non-infringing alternatives added to Intel’s accused products by use of the asserted patents and the share of that value that Intel and VLSI would have agreed Intel would pay in a start-of-infringement hypothetical negotiation” (pp. 22-23). More specifically:
The first step in VLSI’s royalty calculation, as applied to the ʼ373 patent, was to quantify the effect of use of the ʼ373 patent technology on the speed of Intel’s Broadwell and Haswell microprocessors, derived from quantifying its effect on power savings. . . . This quantification was based on testing done by one of VLSI’s experts, Dr. Annavaram. . . . He tested Intel’s Broadwell and Haswell microprocessors and determined that the power savings attributable to the ʼ373 patent technology was 5.45%. . . . Dr. Conte (the VLSI expert whose testimony on equivalents was discussed supra) then translated this power savings benefit into a speed benefit, finding a one-to-one ratio for Intel’s Broadwell and Haswell microprocessors, so that the 5.45% power savings from use of ’373 patent technology provided a 5.45% speed benefit. . . .
Next, VLSI calculated the effect of a speed improvement on the price Intel could fetch for its products, including in its study a number of Intel products, not only the Broadwell and Haswell microprocessors. VLSI’s damages expert, Dr. Sullivan, used a regression model to measure this effect of a speed improvement on price. . . . Dr. Sullivan found that, as relevant here, each 1% improvement in speed was associated with a 0.764% increase in price for Intel’s products. . . .
Then, based on the quantified effect of the ʼ373 patent technology on the speed of Intel’s Broadwell and Haswell microprocessors and the calculated effect of a speed improvement on price for Intel’s products, VLSI made a calculation of the incremental revenue attributable to Intel’s use of the ’373 patent technology in its Broadwell and Haswell microprocessors. Specifically, Dr. Sullivan multiplied the 5.45% speed benefit, by the 0.764% price benefit, by the known total infringing revenues for Intel’s Haswell and Broadwell microprocessors. . . . Dr. Sullivan determined the incremental revenue attributable to use of the ʼ373 patent technology to be $2,115,862,744. . . .
Finally, VLSI had to determine how
Intel and VLSI would have divided up the calculated incremental revenues to set
a royalty Intel would have paid VLSI for the right to use the patent
technology. Reflecting the role of profits (not revenues per se) in the inquiry
. . . Dr. Sullivan concluded that there were no incremental manufacturing costs
incurred by adopting the technology, only other small, incremental costs, e.g.,
costs of making sales . . . . He then inquired into the “relative
contributions” of Intel and VLSI to the production of the incremental revenues
(and hence profits). . . . He did so by considering Intel’s “total spending,”
including sales and marketing, research and development (R&D), and general
and administrative (G&A) costs, seemingly allocating a proportionate share
to the products at issue, and on that basis making “a reasonable estimate of
Intel’s contribution for purposes of the contribution apportionment.” . . . The
Intel contribution figure was 23.8% of total revenue for the two products, with
a 76.2% contribution figure for VLSI (actually, VLSI’s predecessor in interest,
Freescale). . . . Multiplying the VLSI figure by the incremental revenue gave
the reasonably royalty. . . . The net result was a proposed royalty of
$1,611,609,964. . . . The jury awarded $1.5 billion (pp. 23-24).
The court vacates the award based on what it describes as “a readily identifiable error” in Dr. Annavaram’s analysis:
VLSI’s damages model required VLSI to calculate the incremental technical benefit attributable to Intel’s infringement. For the ʼ373 patent, Dr. Annavaram purported to calculate this benefit by calculating the power-savings benefit attributable to the accused processor function of using the multiplexer to change the source of voltage to the C6 SRAM (allowing all cores to go to sleep without loss of re-startup data, thereby saving power)—what the parties before us call using the C6 SRAM. . . . It is undisputed that when Intel’s accused microprocessor enters the Package C7 sleep state, in which all cores are asleep, that function is performed (the C6 SRAM is used), but that it is not performed when Intel’s accused microprocessor enters the Core C7 sleep state, in which individual cores are asleep. . . . Thus, Core C7 and Package C7 are different states, and only the latter reflects the benefits of the infringement at issue. Nevertheless, Dr. Annavaram made use of Core C7 state residency data—data on how much time a processor spends in a given state—in making a choice of inputs into his calculation.
Specifically, he ran experiments on six Intel devices, two with accused Broadwell processors (the other four not accused of infringement of the ’373 patent), to collect data on the residency of the devices in particular states when he put them through selected workloads. He compiled the results in a table, one line of which showed residency in the Core C7 state, while another line residency in the Package C7 state. . . . The residency figures for the former (where any core is shut down, J.A. 18670–71) were close to double those of the latter (where all cores are shut down, J.A. 18671–72). Then, in the next stage of his analysis, which was to employ an Intel analytic tool (Power Model) that estimates power use (and hence power savings) under specified conditions (including residency and workload), Dr. Annavaram used at least the Core C7 figures, and perhaps also the Package C7 figures, in carrying out some kind of “match[ing]” process in order “to select the residency and workload settings in the Intel Power Model.” . . . .
The results of using the Power Model with the selected inputs were the power savings that were crucial to VLSI’s damages calculation. Yet to produce the power-savings results, Dr. Annavaram used inputs that he chose by trying to match (only or in part) data not from use of infringing functionality. That step undermines the reliability of the results as a calculation of power savings from use of the infringing functionality.
We cannot say that this error “could not have changed the result,” namely, the precise amount of damages, so as to render it harmless. . . . The difference between the Core C7 residency data and the Package C7 residency data is on its face significant—75.86% and 75.95% for the Core C7 state versus 41.01% and 57.49% for the Package C7 state. . . . Residency in particular states matters to the power savings . . . and residency inputs chosen in an effort to match non-infringing-state numbers (at least in part) could well affect the bottom line. . . . On this record, we cannot deem this step in the damages calculation harmless as to the bottom-line amount of damages (pp. 25-27).
The court therefore remands for a new trial on damages. Importantly, perhaps, the court does not rule out the use of regression analysis on retrial or in other cases, stating that “Intel, in this court, has not persuasively shown that the regression analysis used to determine price effects of speed improvements is an improper or unreasonable one”—to which the court immediately adds, however, that “VLSI has not adequately elucidated how the last-step cost-and-contribution analysis . . . reasonably establishes the choice Intel and VLSI would have made in the hypothetical negotiation about the sharing of the incremental benefits of implementation of the patent technology. On remand, the opportunity to provide better explanations should be made available” (pp. 27-28).
Finally, in what could possibly be dispositive on remand, the court vacates the lower court’s decision not to consider Intel’s license defense, which was premised on the asserted facts that “(a) in 2012, Intel entered into an agreement with Finjan, in which Finjan granted Intel a perpetual and irrevocable license to patents owned and controlled by Finjan’s 'affiliates' and (b) in July 2020, Fortress acquired 'control' of Finjan, through funds Fortress manages, making VLSI and Finjan 'affiliates' under the license agreement” (p.28). The district court denied leave to amend to assert this defense, but the Federal Circuit states it was an abuse of discretion to conclude that Intel unduly delayed filing the motion to amend, and that the defense is not “so clearly meritless that it allowing even to be pleaded is a futile act” (pp.30-31). The court expresses no opinion on what the result should be when the defense is considered, on remand, stating that under the cited Delaware state law authorities that control interpretation of the 2012 agreement, “we do not think that there is a sufficiently clear answer” regarding “whether VLSI, as a non-party, could be bound,” for the appellate court to make “a determination of futility” (p.33).
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